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1 nv/hz low noise instrumentation amplifier AD8429 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features low noise 1 nv/hz input noise 45 nv/hz output noise high accuracy dc performance (AD8429brz) 90 db cmrr minimum (g = 1) 50 v maximum input offset voltage 0.02% maximum gain accuracy (g = 1) excellent ac specifications 80 db cmrr to 5 khz (g = 1) 15 mhz bandwidth (g = 1) 1.2 mhz bandwidth (g = 100) 22 v/s slew rate thd: ?130 dbc (1 khz, g = 1) versatile 4 v to 18 v dual supply gain set with a single resistor (g = 1 to 10,000) temperature range for specified performance ?40c to +125c applications medical instrumentation precision data acquisition microphone preamplification vibration analysis pin connection diagram top view (not to scale) ?in 1 r g 2 r g 3 +in 4 +v s 8 v out 7 ref 6 ?v s 5 AD8429 09730-001 figure 1. general description the AD8429 is an ultralow noise, instrumentation amplifier designed for measuring extremely small signals over a wide temperature range (?40c to +125c). the AD8429 excels at measuring tiny signals. it delivers ultralow input noise performance of 1 nv/hz. the high cmrr of the AD8429 prevents unwanted signals from corrupting the acqui- sition. the cmrr increases as the gain increases, offering high rejection when it is most needed. the high performance pin configuration of the AD8429 allows it to reliably maintain high cmrr at frequencies well beyond those of typical instrumentation amplifiers. the AD8429 reliably amplifies fast changing signals. its current feedback architecture provides high bandwidth at high gain, for example, 1.2 mhz at g = 100. the design includes circuitry to im- prove settling time after large input voltage transients. the AD8429 was designed for excellent distortion performance, allowing use in demanding applications such as vibration analysis. gain is set from 1 to 10,000 with a single resistor. a reference pin allows the user to offset the output voltage. this feature can be useful to shift the output level when interfacing to a single supply signal chain. the AD8429 performance is specified over the extended industrial temperature range of ?40c to +125c. it is available in an 8-lead plastic soic package. 1000 100 10 1 0.1 noise (nv/ hz) frequency (hz) 1 10 100 1k 10k 100k g = 1 g = 10 g = 100 g = 1k 09730-002 figure 2. rti voltage noise spectral density vs. frequency
AD8429 rev. 0 | page 2 of 20 table of contents features .............................................................................................. 1 applications....................................................................................... 1 pin connection diagram ................................................................ 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 absolute maximum ratings............................................................ 6 thermal resistance ...................................................................... 6 esd caution.................................................................................. 6 pin configuration and function descriptions............................. 7 typical performance characteristics ............................................. 8 theory of operation ...................................................................... 15 architecture ................................................................................ 15 gain selection............................................................................. 15 reference terminal .................................................................... 15 input voltage range................................................................... 16 layout .......................................................................................... 16 input bias current return path ............................................... 17 input protection ......................................................................... 17 radio frequency interference (rfi)........................................ 17 calculating the noise of the input stage................................. 18 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 19 revision history 4/11revision 0: initial version
AD8429 rev. 0 | page 3 of 20 specifications v s = 15 v, v ref = 0 v, t a = 25c, g = 1, r l = 10 k, unless otherwise noted. table 1. a grade b grade parameter test conditions/comments min typ max min typ max unit common-mode rejection ratio (cmrr) cmrr dc to 60 hz with 1 k source imbalance v cm = 10 v g = 1 80 90 db g = 10 100 110 db g = 100 120 130 db g = 1000 134 140 db cmrr at 5 khz v cm = 10 v g = 1 76 80 db g = 10 90 90 db g = 100 90 90 db g = 1000 90 90 db voltage noise, rti v in +, v in ? = 0 v spectral density 1 : 1 khz input voltage noise, e ni 1.0 1.0 nv/hz output voltage noise, e no 45 45 nv/hz peak to peak: 0.1 hz to 10 hz g = 1 2 2 v p-p g = 1000 100 100 nv p-p current noise spectral density: 1 khz 1.5 1.5 pa/hz peak to peak: 0.1 hz to 10 hz 100 100 pa p-p voltage offset 2 input offset, v osi 150 50 v average tc 0.1 1 0.1 0.3 v/c output offset, v oso 1000 500 v average tc 3 10 3 10 v/c offset rti vs. supply (psr) v s = 5 v to 15 v g = 1 90 100 db g = 10 110 120 db g = 100 130 130 db g = 1000 130 130 db input current input bias current 300 150 na average tc 250 250 pa/c input offset current 100 30 na average tc 15 15 pa/c dynamic response small signal bandwidth: C3 db g = 1 15 15 mhz g = 10 4 4 mhz g = 100 1.2 1.2 mhz g = 1000 0.15 0.15 mhz
AD8429 rev. 0 | page 4 of 20 a grade b grade parameter test conditions/comments min typ max min typ max unit settling time 0.01% 10 v step g = 1 0.75 0.75 s g = 10 0.65 0.65 s g = 100 0.85 0.85 s g = 1000 5 5 s settling time 0.001% 10 v step g = 1 0.9 0.9 s g = 10 0.9 0.9 s g = 100 1.2 1.2 s g = 1000 7 7 s slew rate g = 1 to 100 22 22 v/s thd first five harmonics, f = 1 khz, r l = 2 k, v out = 10 v p-p g = 1 ?130 ?130 dbc g = 10 ?116 ?116 dbc g = 100 ?113 ?113 dbc g = 1000 ?111 ?111 dbc thd + n f = 1 khz, r l = 2 k, v out = 10 v p-p g = 100 0.0005 0.0005 % gain 3 g = 1 + (6 k/r g ) gain range 1 10000 1 10000 v/v gain error v out = 10 v g = 1 0.05 0.02 % g > 1 0.3 0.15 % gain nonlinearity v out = ?10 v to +10 v g = 1 to 1000 r l = 10 k 2 2 ppm gain vs. temperature g = 1 2 5 2 5 ppm/c g > 1 ?100 ?100 ppm/c input impedance (pin to ground) 4 1.5||3 1.5||3 g||pf input operating voltage range 5 v s = 4 v to 18 v ?v s + 2.8 +v s ? 2.5 ?v s + 2.8 +v s ? 2.5 v output output swing r l = 2 k ?v s + 1.8 +vs ? 1.2 ?v s + 1.8 +vs ? 1.2 v over temperature ?v s + 1.9 +vs ? 1.3 ?v s + 1.9 +vs ? 1.3 v output swing r l = 10 k ?v s + 1.7 +vs ? 1.1 ?v s + 1.7 +vs ? 1.1 v over temperature ?v s + 1.8 +vs ? 1.2 ?v s + 1.8 +vs ? 1.2 v short-circuit current 35 35 ma reference input r in 10 10 k i in v in +, v in ? = 0 v 70 70 a voltage range ?v s +v s v reference gain to output 1 1 v/v reference gain error 0.01 0.05 0.01 0.05 %
AD8429 rev. 0 | page 5 of 20 a grade b grade parameter test conditions/comments min typ max min typ max unit power supply operating range 4 18 4 18 v quiescent current 6.7 7 6.7 7 ma t = 125c 9 9 ma temperature range for specified performance ?40 +125 ?40 +125 c 1 total voltage noise = (e ni 2 + (e no /g) 2 + e rg 2 ). see the theory of operation section for more information. 2 total rti v os = (v osi ) + (v oso /g). 3 these specifications do not include the tolerance of the external gain setting resistor, r g . for g > 1, add r g errors to the specifications given in this table. 4 differential and common-mode input impedance ca n be calculated from the pin impedance: z diff = 2(z pin ); z cm = z pin /2. 5 input voltage range of the AD8429 input stag e only. the input range can depend on the common-mode voltage, differential voltag e, gain, and reference voltage. see the section for more details. input voltage range
AD8429 rev. 0 | page 6 of 20 absolute maximum ratings table 2. parameter rating supply voltage 18 v output short-circuit current duration indefinite maximum voltage at Cin, +in 1 v s differential input voltage 1 gain 4 v s 4 > gain > 50 50 v/gain gain 50 1 v maximum voltage at ref v s storage temperature range ?65c to +150c specified temperature range ?40c to +125c maximum junction temperature 140c esd human body model 3.0 kv charge device model 1.5 kv machine model 0.2 kv 1 for voltages beyond these limits, use input protection resistors. see the theory of operation section for more information. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for a device in free air using a 4-layer jedec printed circuit board (pcb). table 3. package ja unit 8-lead so ic 121 c/w esd caution
AD8429 rev. 0 | page 7 of 20 pin configuration and fu nction descriptions top view (not to scale) ?in 1 r g 2 r g 3 +in 4 +v s 8 v out 7 ref 6 ?v s 5 AD8429 09730-003 figure 3. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 ?in negative input terminal. 2, 3 r g gain setting terminals. place resistor across the r g pins to set the gain. g = 1 + (6 k/r g ). 4 +in positive input terminal. 5 ?v s negative power supply terminal. 6 ref reference voltage terminal. drive this terminal with a low impedance voltage source to level shift the output. 7 v out output terminal. 8 +v s positive power supply terminal.
AD8429 rev. 0 | page 8 of 20 typical performance characteristics t = 25c, v s = 15, v ref = 0, r l = 10 k, unless otherwise noted. 15 ?15 ?10 ?5 0 5 10 ?15 ?10 ?5 0 5 10 15 common-mode voltage (v) output voltage (v) g = 1 v s = 15v v s = 12v v s = 5v 09730-010 figure 4. input common-mode voltage vs. output voltage, dual supply, v s = 5 v, 12 v, 15 v (g = 1) 15 ?15 ?10 ?5 0 5 10 ?15 ?10 ?5 0 5 10 15 common-mode voltage (v) output voltage (v) g = 100 v s = 15v v s = 12v v s = 5v 09730-011 figure 5. input common-mode voltage vs. output voltage, dual supply, v s = 5 v, 12 v, 15 v (g = 100) ?12.28v +12.60v ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 12 14 input bias current (na) common-mode voltage (v) 09730-068 figure 6. input bias current vs. common-mode voltage frequency (hz) 0 20 40 60 80 100 120 140 160 1 10 100 1k 10k 100k 1m positive psrr (db) gain = 1 gain = 1000 gain = 10 gain = 100 09730-069 figure 7. positive psrr vs. frequency frequency (hz) 0 20 40 60 80 100 120 140 negative psrr (db) 160 1 10 100 1k 10k 100k 1m gain = 1 gain = 1000 gain = 10 gain = 100 09730-070 figure 8. negative psrr vs. frequency ?30 ?20 ?10 0 10 20 30 40 50 60 70 100 1k 10k 100k 1m 10m 100m gain (db) frequency (hz) gain = 1 gain = 1000 gain = 100 gain = 10 v s = 15v 09730-017 figure 9. gain vs. frequency
AD8429 rev. 0 | page 9 of 20 frequency (hz) 1 0 20 40 60 80 100 120 140 160 cmrr (db) 10 100 1k 10k 100k 1m g = 1 g = 10 g = 100 g = 1k bandwidth limited 09730-110 figure 10. cmrr vs. frequency frequency (hz) 1 10 100 1k 10k 1m 100k 0 20 40 60 80 100 120 140 cmrr (db) g = 1 g = 10 g = 100 g = 1k bandwidth limited 09730-111 figure 11. cmrr vs. frequency, 1 k source imbalance 0 2 4 6 8 10 12 0 100 200 300 400 500 600 700 change in input offset voltage (v) warm-up time (s) 09730-112 figure 12. change in input offset voltage (v osi ) vs. warm-up time 40 ?20 ?10 0 10 20 30 3.0 0 0.5 1.0 1.5 2.0 2.5 ?45 ?15 15 45 75 105 135 ?30 0 30 60 90 120 input bias current (na) input offset current (na) temperature (c) i b + i b ? i os 09730-019 figure 13. input bias current and input offset current vs. temperature 40 30 20 ?20 ?30 ?40 ?50 ?60 ?40 ?25 ?10 5 20 35 temperature (c) 50 65 80 95 110 125 10 ?10 cmrr (v/v) 0 normalized at 25c gain = 1 09730-114 figure 14. cmrr vs. temperature (g = 1), normalized at 25c 10.0 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 ?50 ?10 130110 90 70503010 ?30 supply current (ma) temperature (c) 09730-022 figure 15. supply current vs. temperature (g = 1)
AD8429 rev. 0 | page 10 of 20 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 short-circuit current (ma) temperature (c) i short+ i short? 09730-023 figure 16. short-circuit current vs. temperature (g = 1) 0 30 25 20 15 10 5 ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 slew rate (v/s) temperature (c) +sr ?sr 09730-024 figure 17. slew rate vs. temperature, v s = 15 v (g = 1) 0 25 20 15 10 5 ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 slew rate (v/s) temperature (c) +sr ?sr 09730-025 figure 18. slew rate vs. temperature, v s = 5 v (g = 1) + v s ?v s +0.5 +1.0 +1.5 +2.0 +2.5 ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 41 16 14 12 10 86 input voltage (v) referred to supply voltages supply voltage (v s ) 8 ?40c +25c +85c +125c 09730-026 figure 19. input voltage limit vs. supply voltage + v s ?v s +0.4 +0.8 +1.2 +1.6 +2.0 ?0.4 ?0.8 ?1.2 41 16 14 12 10 86 input voltage (v) referred to supply voltages supply voltage (v s ) 8 ?40c +25c +85c +125c 09730-027 figure 20. output voltage swing vs. supply voltage, r l = 10 k + v s ?v s +0.4 +0.8 +1.2 +1.6 +2.0 ?0.4 ?0.8 ?1.2 41 16 14 12 10 86 input voltage (v) referred to supply voltages supply voltage (v s ) 8 ?40c +25c +85c +125c 09730-028 figure 21. output voltage swing vs. supply voltage, r l = 2 k
AD8429 rev. 0 | page 11 of 20 15 10 5 0 ?5 ?10 ?15 100 100k 10k 1k output voltage swing (v) load ( ? ) ?40c +25c +85c +125c v s = 15v 09730-029 figure 22. output voltage swing vs. load resistance 10 10m 1m 100 output voltage swing (v) referred to supply voltages output current (a) v s = 15v + v s ?v s +0.4 +0.8 +1.2 +1.6 +2.0 ?0.4 ?0.8 ?1.2 ?1.6 ?40c +25c +85c +125c 09730-030 figure 23. output voltage swing vs. output current ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 nonlinearity (ppm/div) output voltage (v) gain = 1 ?10?8?6?4?20246810 09730-083 figure 24. gain nonlinearity (g = 1), r l = 10 k ?10 ?10?8?6?4?20246810 ?8 ?6 ?4 ?2 0 2 4 6 8 10 nonlinearity (ppm/div) output voltage (v) gain = 1000 0 9730-084 figure 25. gain nonlinearity (g = 1000), r l = 10 k 1000 100 10 1 0.1 noise (nv/ hz) frequency (hz) 1 10 100 1k 10k 100k g = 1 g = 10 g = 100 g = 1k 09730-126 figure 26. rti voltage noise spectral density vs. frequency 1s/div gain = 1000, 100nv/div gain = 1, 2 v/div 09730-086 figure 27. 0.1 hz to 10 hz rti voltage noise (g = 1, g = 1000)
AD8429 rev. 0 | page 12 of 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 10 100 1k 10k 100k noise (pa/ hz) frequency (hz) 09730-087 figure 28. current noise spectral density vs. frequency 50pa/div 1s/div 09730-088 figure 29. 0.1 hz to 10 hz current noise 0 5 10 15 20 25 30 100 1k 10k 100k 1m 10m output voltage (v p-p) frequency (hz) g = 1 v s = 15v v s = 5v 09730-089 figure 30. large signal frequency response 5v/div 0.002%/div 750ns to 0.01% 872ns to 0.001% time (s) 2s/div 09730-090 figure 31. large signal pulse response and settling time (g = 1), 10 v step, v s = 15 v 5v/div 2s/div 640ns to 0.01% 896ns to 0.001% time (s) 0.002%/div 09730-091 figure 32. large signal pulse response and settling time (g = 10), 10 v step, v s = 15 v 5v/div 2s/div 840ns to 0.01% 1152ns to 0.001% time (s) 0.002%/div 09730-040 figure 33. large signal pulse response and settling time (g = 100), 10 v step, v s = 15 v
AD8429 rev. 0 | page 13 of 20 5v/div 10s/div 5.04s to 0.01% 6.96s to 0.001% time (s) 0.002%/div 09730-041 figure 34. large signal pulse response and settling time (g = 1000), 10 v step, v s = 15 v g = 1 1s/div 50mv/div 09730-042 figure 35. small signal response (g = 1), r l = 10 k, c l = 100 pf 20mv/div g = 10 1s/div 09730-043 figure 36. small signal response (g = 10), r l = 10 k, c l = 100 pf 20mv/div g = 100 1s/div 09730-044 figure 37. small signal response (g = 100), r l = 10 k, c l = 100 pf 20mv/div g = 1000 10s/div 09730-045 figure 38. small signal response (g = 1000), r l = 10 k, c l = 100 pf g = 1 1s/div 50mv/div no load c l = 100pf c l = 147pf 0 9730-093 figure 39. small signal response with various capacitive loads (g = 1), r l = infinity
AD8429 rev. 0 | page 14 of 20 0 200 400 600 800 1000 1200 1400 2 4 6 8 10 12 14 16 18 20 settling time (ns) step size (v) settled to 0.001% settled to 0.01% 09730-092 figure 40. settling time vs. step size (g = 1) 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1k 10k 100k amplitude (percentage of fundamental) frequency (hz) no load 2k ? load 600 ? load g = 1, second harmonic v out = 10v p-p 09730-096 figure 41. second harmonic distortion vs. frequency (g = 1) 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1k 10k 100k amplitude (percentage of fundamental) frequency (hz) no load 2k? load 600 ? load g = 1, third harmonic v out = 10v p-p 09730-097 figure 42. third harmonic distortion vs. frequency (g = 1) 0.0001 0.001 0.01 0.1 1 10 100 1k 10k 100k amplitude (percentage of fundamental) frequency (hz) no load 2k? load 600? load g = 1000, second harmonic v out = 10v p-p 09730-098 figure 43. second harmonic distortion vs. frequency (g = 1000) 0.0001 0.001 0.01 0.1 1 10 100 1k 10k 100k amplitude (percentage of fundamental) frequency (hz) no load 2k? load 600? load g = 1000, third harmonic v out = 10v p-p 09730-099 figure 44. third harmonic distortion vs. frequency (g = 1000) 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1k 10k 100k thd (%) frequency (hz) gain = 1 gain = 100 v out = 10v p-p r l 2k ? gain = 10 gain = 1000 09730-100 figure 45. thd vs. frequency
AD8429 rev. 0 | page 15 of 20 theory of operation a3 a1 a2 q2 q1 c1 c2 +in ?in +v s ?v s +v s ?v s +v s ?v s r3 5k? r4 5k? r5 5k? rg? +v s ?v s v out ref node 1 node 2 i b compensation i b compensation r g v b ii +v s ?v s +v s ?v s r6 5k? rg+ r2 3k ? r1 3k ? 09730-058 figure 46. simpli fied schematic architecture the AD8429 is based on the classic 3-op - amp topology. this topology has two stages: a preamplifier to provide differential amplification followed by a difference amplifier that removes the common-mode voltage and provides additional amplifica- tion. figure 46 shows a simplified schematic of the AD8429. the first stage works as follows. to keep its two inputs matched, amplifier a1 must keep the collector of q1 at a constant voltage. it does this by forcing rg? to be a precise diode drop from Cin. similarly, a2 forces rg+ to be a constant diode drop from +in. therefore, a replica of the differential input voltage is placed across the gain setting resistor, r g . the current that flows through this resistance must also flow through the r1 and r2 resistors, creating a gained differential signal between the a2 and a1 outputs. the second stage is a g = 1 difference amplifier, composed of amplifier a3 and the r3 through r6 resistors. this stage removes the common-mode signal from the amplified differential signal. the transfer function of the AD8429 is v out = g ( v in+ ? v in? ) + v ref where: g r g k 6 1 += gain selection placing a resistor across the r g terminals sets the gain of the AD8429, which can be calculated by referring to tabl e 5 or by using the following gain equation: 1 k 6 ? = g r g table 5. gains achieved using 1 resistors 1% standard table value of r g calculated gain 6.04 k 1.993 1.5 k 5.000 665 10.02 316 19.99 121 50.59 60.4 100.3 30.1 200.3 12.1 496.9 6.04 994.4 3.01 1994 the AD8429 defaults to g = 1 when no gain resistor is used. add the tolerance and gain drift of the r g resistor to the specifications of the AD8429 to determine the total gain accu- racy of the system. when the gain resistor is not used, gain error and gain drift are minimal. r g power dissipation the AD8429 duplicates the differential voltage across its inputs onto the r g resistor. choose an r g resistor size sufficient to handle the expected power dissipation. reference terminal the output voltage of the AD8429 is developed with respect to the potential on the reference terminal. this is useful when the output signal must be offset to a precise midsupply level. for example, a voltage source can be tied to the ref pin to level shift the output, allowing the AD8429 to drive a single-supply adc. the ref pin is protected with esd diodes and should not exceed either +v s or ?v s by more than 0.3 v.
AD8429 rev. 0 | page 16 of 20 for best performance, maintain a source impedance to the ref terminal that is well below 1 . as shown in figure 46 , the reference terminal, ref, is at one end of a 5 k resistor. additional impedance at the ref terminal adds to this 5 k resistor and results in amplification of the signal connected to the positive input. the amplification from the additional r ref can be calculated as follows: 2(5 k + r ref )/(10 k + r ref ) only the positive signal path is amplified; the negative path is unaffected. this uneven amplification degrades cmrr. incorrect v correct AD8429 op1177 + ? v ref AD8429 ref 09730-059 figure 47. driving the reference pin input voltage range figure 4 and figure 5 show the allowable common-mode input voltage ranges for various output voltages and supply voltages. the 3-op - amp architecture of the AD8429 applies gain in the first stage before removing common-mode voltage with the difference amplifier stage. internal nodes between the first and second stages (node 1 and node 2 in figure 46 ) experience a combination of a gained signal, a common-mode signal, and a diode drop. this combined signal can be limited by the voltage supplies even when the individual input and output signals are not limited. layout to ensure optimum performance of the AD8429 at the pcb level, care must be taken in the design of the board layout. the pins of the AD8429 are arranged in a logical manner to aid in this task. 8 7 6 5 1 2 3 4 ?in r g r g +v s v out ref ?v s +in top view (not to scale) AD8429 09730-060 figure 48. pinout diagram common-mode reection ratio over frequency poor layout can cause some of the common-mode signals to be converted to differential signals before reaching the in-amp. such conversions occur when one input path has a frequency response that is different from the other. to maintain high cmrr over frequency, closely match the input source impedance and capacitance of each path. place additional source resistance in the input path (for example, for input protection) close to the in-amp inputs, which minimizes their interaction with parasitic capacitance from the pcb traces. parasitic capacitance at the gain setting pins can also affect cmrr over frequency. if the board design has a component at the gain setting pins (for example, a switch or jumper), choose a component such that the parasitic capacitance is as small as possible. power supplies and grounding use a stable dc voltage to power the instrumentation amplifier. noise on the supply pins can adversely affect performance. see the psrr performance curves in figure 9 and figure 10 for more information. place a 0.1 f capacitor as close as possible to each supply pin. because the length of the bypass capacitor leads is critical at high frequency, surface-mount capacitors are recommended. a parasitic inductance in the bypass ground trace works against the low impedance created by the bypass capacitor. as shown in figure 49 , a 10 f capacitor can be used farther away from the device. for larger value capacitors, intended to be effective at lower frequencies, the current return path distance is less critical. in most cases, this capacitor can be shared by other precision integrated circuits. AD8429 + v s +in ?in load r g ref 0.1f 10f 0.1f 10f ?v s v out 09730-061 figure 49. supply decoupling, ref, and output referred to local ground a ground plane layer is helpful to reduce parasitic inductances. this minimizes voltage drops with changes in current. the area of the current path is directly proportional to the magnitude of parasitic inductances and, therefore, the impedance of the path at high frequency. large change s in currents in an inductive decoupling path or ground return create unwanted effects, due to the coupling of such chan ges into the amplifier inputs. because load currents flow from the supplies, the load should be connected at the same physical location as the bypass capa- citor grounds. reference pin the output voltage of the AD8429 is developed with respect to the potential on the reference terminal. ensure that ref is tied to the appropriate local ground.
AD8429 rev. 0 | page 17 of 20 input bias current return path the input bias current of the AD8429 must have a return path to ground. when using a floating source without a current return path, such as a thermocouple, create a current return path, as shown in figure 50 . thermocouple +v s ref ?v s AD8429 capacitively coupled +v s ref c c ?v s AD8429 transformer +v s ref ?v s AD8429 incorrect capacitively coupled +v s ref c r r c ?v s AD8429 1 f high-pass = 2 rc thermocouple +v s ref ?v s 10m ? AD8429 transformer +v s ref ?v s AD8429 correct 09730-062 figure 50. creating an input bias current return path input protection do not allow the inputs of the AD8429 to exceed the ratings stated in the absolute maximum ratings section of this data sheet. if this cannot be done, protection circuitry can be added in front of the AD8429 to limit the current into the inputs to a maximum current, i max . input voltages beyond the rails if voltages beyond the rails are expected, use an external resistor in series with each input to limit current during overload condi- tions. the limiting resistor at the input can be computed from max supply in protect i vv r | | ? noise sensitive applications may require a lower protection resis- tance. low leakage diode clamps, such as the bav199, can be used at the inputs to shunt current away from the AD8429 inputs, thereby allowing smaller protection resistor values. to ensure current flows primarily through the external protection diodes, place a small value resistor, such as a 33 , between the diodes and the AD8429. simple method low noise method +v s AD8429 r protect r protect ?v s i v in+ + ? v in? + ? +v s + v s AD8429 r protect 33? 33? r protect ?v s ?v s i v in+ + ? v in? + ? +v s ?v s 09730-066 figure 51. protection for voltages beyond the rails large differential input voltage at high gain if large differential voltages at high gain are expected, use an external resistor in series with each input to limit current during overload conditions. the limiting resistor at each input can be computed by using the following equation: g max diff protect r i v r ? ? ? ? ? ? ? ? ? ? v1 2 1 noise sensitive applications may require a lower protection resis- tance. low leakage diode clamps, such as the bav199, can be used across the inputs to shunt current away from the AD8429 inputs and, therefore, allow smaller protection resistor values. AD8429 r protect r protect i v diff + ? AD8429 r protect r protect i v diff + ? simple method low noise method 09730-067 figure 52. protection for large differential voltages i max the maximum current into the AD8429 inputs, i max , depends on time and temperature. at room temperature, the device can withstand a current of 10 ma for at least one day. this time is cumulative over the life of the device. radio frequency interference (rfi) rf rectification is often a problem when amplifiers are used in applications that have strong rf signals. the disturbance can appear as a small dc offset voltage. high frequency signals can be filtered with a low-pass rc network placed at the input of the instrumentation amplifier, as shown in figure 53 .
AD8429 rev. 0 | page 18 of 20 r r AD8429 + v s +in ?in 0.1f 10f 10f 0.1f ref v out ?v s r g c d 10nf c c 1nf c c 1nf 4.02k ? 4.02k ? 09730-063 figure 53. rfi suppression the filter limits the input signal bandwidth, according to the following relationship: )2(2 1 c d diff ccr uency filterfreq + = c cm rc uency filterfreq 2 1 = where c d 10 c c . c d affects the difference signal, and c c affects the common-mode signal. choose values of r and c c that minimize rfi. a mismatch between r c c at the positive input and r c c at the negative input degrades the cmrr of the AD8429. by using a value of c d that is one magnitude larger than c c , the effect of the mismatch is reduced, and performance is improved. resistors add noise; therefore, the choice of resistor and capacitor values depends on the desired tradeoff between noise, input impedance at high frequencies, and rfi immunity. the resistors used for the rfi filter can be the same as those used for input protection. calculating the noise of the input stage r2 r g r1 senso r AD8429 09730-064 figure 54. source resistance from sensor and protection resistors the total noise of the amplifier front end depends on much more than the 1 nv/hz specification of this data sheet. there are three main contributors: the source resistance, the voltage noise of the instrumentation amplifier, and the current noise of the instrumentation amplifier. in the following calculations, noise is referred to the input (rti). in other words, everything is calculated as if it appeared at the amplifier input. to calculate the noise referred to the amplifier output (rto), simply multiply the rti noise by the gain of the instrumentation amplifier. source resistance noise any sensor connected to the AD8429 has some output resistance. there may also be resistance placed in series with inputs for pro- tection from either overvoltage or radio frequency interference. this combined resistance is labeled r1 and r2 in figure 54 . any resistor, no matter how well made, has an intrinsic level of noise. this noise is proportional to the square root of the resistor value. at room temperature, the value is approximately equal to 4 nv/hz (resistor value in k). for example, assuming that the combined sensor and protec- tion resistance on the positive input is 4 k, and on the negative input is 1 k, the total noise from the input resistance is ( ) ( ) =+=+ 16641444 2 2 8.9 nv/hz voltage noise of the instrumentation amplifier the voltage noise of the instrumentation amplifier is calculated using three parameters: the device input noise, output noise, and the r g resistor noise. it is calculated as follows: total voltage noise = ( ) ( )( ) 2 2 2 / resistorrofnoise noiseinputgnoise output g + + for example, for a gain of 100, the gain resistor is 60.4 . there- fore, the voltage noise of the in-amp is () ( ) 2 22 0604.041100/45 ++ = 1.5 nv/hz current noise of the instrumentation amplifier current noise is calculated by multiplying the source resistance by the current noise. for example, if the r1 source resistance in figure 54 is 4 k, and the r2 source resistance is 1 k, the total effect from the current noise is calculated as follows: ()() ( ) 2 2 5.115.14 + = 6.2 nv/hz total noise density calculation to determine the total noise of the in-amp, referred to input, combine the source resistance noise, voltage noise, and current noise contribution by the sum of squares method. for example, if the r1 source resistance in figure 54 is 4 k, the r2 source resistance is 1 k, and the gain of the in-amps is 100, the total noise, referred to input, is 222 2.65.19.8 ++ = 11.0 nv/hz
AD8429 rev. 0 | page 19 of 20 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 55. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) ordering guide model 1 temperature range package description package option AD8429arz ?40c to +125c 8-lead soic_n r-8 AD8429arz-r7 ?40c to +125c 8-lead soic_n, 7 tape and reel r-8 AD8429brz ?40c to +125c 8-lead soic_n r-8 AD8429brz-r7 ?40c to +125c 8-lead soic_n, 7 tape and reel r-8 1 z = rohs compliant part.
AD8429 rev. 0 | page 20 of 20 notes ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09730-0-4/11(0)

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